Dynamic logic circuits typically perform logic operations using properties of capacitive storage nodes. Such logic circuits are commonly utilized in processor logic, and are now being utilized in memory circuits.
The operations of a typical dynamic logic circuit fall into two distinct phases: a precharge phase and an evaluation phase. A clock signal provides logic synchronization and also allows predefined charge states to be established in a precharge phase of the clock cycle. One or more outputs are produced during a predetermined evaluation portion of the clock cycle.
Dynamic logic circuits are often contracted from complementary metal oxide semiconductor (CMOS) field effect transistors, due to their low power dissipation. A logic cell commonly used in dynamic CMOS logic circuits includes a precharge device (usually a single PMOS transistor) with a clock input to which a periodic clock signal is applied, a logic circuit (usually an NMOS circuit) with one or more logic inputs for receiving input signals, and an evaluation device (usually a single NMOS transistor) with a clock input for receiving the clock signal. During a precharge phase, the clock signal is at a logic low state ("0"), such that an output is connected to a supply voltage (V.sub.DD) through the PMOS precharge transistor and precharged to a logic high ("1") state. The evaluation phase occurs when the clock signal transitions to a logic high state, turning off the PMOS precharge transistor and turning on the NMOS evaluation transistor. Depending on the input signal value(s), the output either is discharged to a logic low state or remains at a logic high state.
Thus, as described above, a typical dynamic logic circuit is driven by a clock signal to synchronize and to effect the associated logical function implemented in the logic circuit. The clock signal also serves to precharge the logic circuit so that it is ready for the next series of signal inputs.
One problem with utilizing a clock signal to synchronize logical operations within an integrated circuit, which may include logic circuits cascaded as a plurality of stages, is that the clock signal may be subject to noise and clock skew while being transmitted throughout the integrated circuit, resulting in a distorted and inaccurate response at a given one of the cascaded logic circuits.
A proposed solution to the foregoing problem is to combine a reset circuit with a logic circuit, the reset circuit being operative to precharge the logic circuit to a ready state so that it can accept input signals and responsively perform logical operations in a coordinated fashion. Examples of such conventional self-resetting dynamic CMOS logic circuits are described in U.S. Pat. No. 4,751,407 to Powell, U.S. Pat. No. 5,465,060 to Pelella, U.S. Pat. No. 5,467,037 to Kumar et al., U.S. Pat. No. 5,543,735 to Lo, U.S. Pat. No. 5,550,490 to Durham et al., U.S. Pat. No. 5,576,644 to Pelella, and U.S. Pat. No. 5,650,733 Covino.
The output signal produced by such a self-resetting circuit may be directly affected by the input pulse width. When such self-resetting dynamic logic circuits are cascaded in a plurality of stages in an integrated circuit such as a processor or memory, there may be a need to provide a reset (or precharge) timing margin for each circuit in order to guarantee stable reset operation. Along a cascade of stages, the need to provide a reset margin may cause respective stage output pulse widths to undesirably increase down the chain of stages. For this and other reasons, it may be difficult to control the timing of the integrated circuit.